1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing that semiconductor device, and more specifically to a semiconductor device comprising a high frequency circuit with an inductor.
2. Description of the Background Art
One example of the structure of a semiconductor device with a high frequency circuit will be described with reference to FIG. 35. FIG. 35 is a block diagram of the structure of a semiconductor device 90 that has the function of receiving radio signals in the radio-frequency range of 10 kHz to 100 GHz and outputting audio signals.
As shown in FIG. 35, the semiconductor device 90 comprises at least a RF circuit portion 91 for demodulating radio signals received, a logic portion 92 for processing and translating those signals demodulated by the RF circuit portion 91 into audio signals, and a memory cell portion 93 for storing necessary data for signal processing in the RF circuit portion 91 and the logic portion 92. The semiconductor device 90 is connected to an antenna unit 94 for receiving radio signals and a sound output device 95 for outputting audio signals.
So-called high-frequency circuits, including the RF circuit portion 91, comprise an inductor (inductance element) in addition to a resistor and a capacitor. Since the inductor acts to advance the phase of high frequency current, the use of such an inductor against the capacitor which acts to delay the phase of high frequency current, provides matching of the high frequency current.
An inductor L1 in the RF circuit portion 91 illustrated in FIG. 35 has a parasitic capacitor C1 which is grounded through a resistor R1. The resistor R1 is the resistance of a semiconductor substrate on which the RF circuit portion 91 is formed. Very low or high values of such resistance offer no problem, but certain types of substrates have such a resistance (e.g., around 100 xcexa9cm) that consumes power because of electrostatically induced power dissipation.
FIG. 36 is a perspective view of the structure of the inductor L1. As shown in FIG. 36, the inductor L1 is formed by winding wiring in spiral form and thus hereinafter referred to as a xe2x80x9cspiral inductor SIxe2x80x9d. The center of the spiral, which is a first end of the spiral inductor SI, is connected to underlying wiring WL through a contact portion CP which passes through an interlayer insulation film not shown.
As has been described, it is common for semiconductor devices each with a high-frequency circuit to comprise a so-called spiral inductor. One side of the spiral inductor has a dimension of 100 to 200 xcexcm, and an insulation layer whose dimensions are commensurate with those of the spiral inductor is provided in the surface of a wiring board under the spiral inductor. There is, however, a problem that the insulation layer with an excessively large area hampers miniaturization of the semiconductor devices, whereas the insulation layer with an excessively small area makes unignorable electrostatically induced power dissipation and electromagnetically induced power dissipation due to the spiral inductor.
A first aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate; a first isolation oxide film provided in a main surface of the semiconductor substrate; and an inductance element provided on a region in which the first isolation oxide film is formed with an interlayer insulation film therebetween, wherein the first isolation oxide film is provided so that a horizontal distance between an end surface of the first isolation oxide film and a nearest one of end surfaces of the inductance element is not less than a vertical distance between a lower surface of the inductance element, which is opposed to the first isolation oxide film, and a surface of the semiconductor substrate.
A second aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate; a first isolation oxide film provided in a main surface of the semiconductor substrate; an inductance element provided on a region in which the first isolation oxide film is formed with an interlayer insulation film therebetween; and a conductor layer provided at a height between the first isolation oxide film and the inductance element; wherein the conductor layer is provided so that a horizontal distance between an end surface of the conductor layer and a nearest one of end surfaces of the inductance element is not less than a vertical distance between a lower surface of the inductance element and a surface of the semiconductor substrate.
A third aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate; a first isolation oxide film provided in a main surface of the semiconductor substrate; an inductance element provided on a region in which the first isolation oxide film is formed with an interlayer insulation film therebetween; and a dummy pattern region provided around the first isolation oxide film and divided by a second isolation oxide film having a smaller width than the first isolation oxide film in a plan view.
According to a semiconductor device of a fourth aspect of the present invention, the first isolation oxide film is provided so that a horizontal distance between each end surface of the first isolation oxide film and a nearest one of end surfaces of the inductance element is not less than a vertical distance between the lower surface of the inductance element and the surface of the semiconductor substrate.
According to a semiconductor device of a fifth aspect of the present invention, the semiconductor substrate is an SOI substrate comprising a substrate portion to be a foundation, a buried oxide film provided on the substrate portion, and an SOI layer provided on the buried oxide film; and the vertical distance is a vertical distance between the lower surface of the inductance element and a surface of the substrate portion.
According to a semiconductor device of a sixth aspect of the present invention, the first isolation oxide film includes a first portion having a first width and extending in a depth direction with respect to a surface of the buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending in a depth direction with respect to the surface of the buried oxide film to reach the buried oxide film; and the end surface of the first isolation oxide film is an surface of the second portion.
According to a semiconductor device of a seventh aspect of the present invention, the first isolation oxide film has a predetermined width and extends in a depth direction with respect to a surface of the buried oxide film.
According to a semiconductor device of an eighth aspect of the present invention, the first isolation oxide film is rectangular in shape in a plane view; and the dummy pattern region has a width 5% or more of a length of a short side of the first isolation oxide film.
According to a semiconductor device of a ninth aspect of the present invention, the dummy pattern region includes a field portion defined by the second isolation oxide film; and an area ratio of the second isolation oxide film in the dummy pattern region to the field portion is set to be approximately 1:1.
In the semiconductor device of the first aspect, the first isolation oxide film is provided so that the horizontal distance between each end surface of the first isolation oxide film and a nearest one of end surfaces of the inductance element is not less than the vertical distance between the lower surface of the inductance element and the surface of the semiconductor substrate. This reduces parasitic capacitance between the inductance element and the semiconductor substrate in the vicinity of the end surfaces of the first isolation oxide film, resulting in a reduction in electrostatically induced power dissipation. Further, electromagnetically induced power dissipation can be reduced by decreasing perspective angles which are formed when the inductance element is viewed from the semiconductor substrate in the vicinity of the end surfaces of the first isolation oxide film.
In the semiconductor device of the second aspect, the conductor layer is provided so that the horizontal distance between each end surface of the conductor layer and a nearest one of end surfaces of the inductance element is not less than the vertical distance between the lower surface of the inductance element and the substrate of the semiconductor substrate. This reduces parasitic capacitance between the inductance element and the conductor layer, resulting in a reduction in electrostatically induced power dissipation. Further, electromagnetically induced power dissipation can be reduced by decreasing perspective angles which are formed when the inductance element is viewed from the edge portions of the conductor layer.
The semiconductor device of the third aspect comprises, around the first isolation oxide film, the dummy pattern region which is divided by the second isolation oxide film having a small width in the plane view. Thus, when the first isolation oxide film is formed by CMP, dishing in the first isolation oxide film would not extend beyond the dummy pattern region. This prevents the extension of dishing to the transistor formation regions.
In the semiconductor device of the fourth aspect, electrostatically induced power dissipation and electromagnetically induced power dissipation can be reduced in either structure: the structure wherein the conductor layer is provided at a height between the first isolation oxide film and the inductance element: and the structure wherein the dummy pattern region including the second isolation oxide film is provided around the first isolation oxide film.
In the semiconductor device of the fifth aspect, the semiconductor substrate is the SOI substrate. This ensures element isolation and allows the use of a minimal width of the isolation oxide film, the width being determined by micro-lithography. Thus, downsizing of the device can be achieved.
In the semiconductor device of the sixth aspect, the first isolation oxide film is a complete isolation oxide film including in part a so-called partial isolation oxide film. The first isolation oxide film is comprised of a first portion having the first width and extending in the depth direction with respect to the surface of the buried oxide film, and a second portion having the second width smaller than the first width and being formed under the first portion, extending in the depth direction with respect to the surface of the buried oxide film to reach that buried oxide film. In such a semiconductor device that provides element isolation with a partial isolation oxide film, therefore, the first isolation oxide film can be formed in the process of forming the partial isolation oxide film to provide element isolation. This simplifies the manufacturing.
In the semiconductor device of the seventh aspect, the first isolation oxide film is a so-called complete isolation oxide film which has a predetermined width and extends in the depth direction with respect to the surface of the buried oxide film. In such a semiconductor device that provides element isolation with a complete isolation oxide film, therefore, the first isolation oxide film can be formed in the process of forming the complete isolation oxide film to provide element isolation. This simplifies the manufacturing process. Further, this first isolation film has no area of thin in thickness and high resistance, unlike those including in part the partial isolation oxide film. This allows a reduction in electromagnetically induced power dissipation in that film.
In the semiconductor device of the eighth aspect, the dummy pattern region has the width 5% or more of the length of the short sides of the first isolation oxide film. This prevents dishing from extending beyond the dummy pattern region.
In the semiconductor device of the ninth aspect, the area ratio of the second isolation oxide film in the dummy pattern region to the field portion is set to be approximately 1:1 in the plane view. This effectively prevents dishing from extending beyond the dummy pattern region.
An object of the present invention is to provide a semiconductor device with a spiral inductor, which determines the area of an insulation layer to be provided in the surface of a wiring board under the spiral inductor.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.